1. Field of the Invention
This invention relates to the general field of copper-based interconnections for integrated circuits.
2. Description of the Prior Art
The industry need for increased integrated circuit (IC) chip performance beyond 0.25 μm technology in conjunction with decreasing feature size is causing migration of interconnect systems to lower resistivity Cu based-conductors. Modem commercial Cu IC chips, which usually contain 4 to 8 levels of Cu interconnections, are generally fabricated by a single and/or dual damascene process. The two most important on-chip interconnection reliability issues are electromigration and stress induced voiding in the Cu interconnect circuit elements. Electromigration in copper metallization for IC chips has been extensively studied. Electromigration and stress induced voiding are the motion of atoms by diffusion in an electrical field and stress gradient, respectively. When an interconnect is electrically stressed in a dc current, the drifting of Cu atoms can cause mass depletion (resulting in a void or an open circuit) or accumulation (resulting in an extrusion or a short-circuit) at the locations where the microstructure and/or materials are varied such that an imbalance of atom flux exists. Hu et al. (Proceedings of 1999 International Interconnect Technology, p. 197) reported that Cu mass transport in Cu interconnects occurs primarily at the surface interface, not at grain boundaries. In Cu interconnection structures the top surface of a line is generally covered by an insulator, e.g., silicon nitride, and the bottom and sides of the line are covered with a liner, e.g. TaN/Ta. The Cu lines are connected to other lines through inter-level vias. Since diffusion at the top Cu/silicon nitride interface is dominant in Cu, then the electromigration flux is constrained to the top interface within an area of δsw, where δs is the effective thickness of the interface region and w is the line width. The relative amount of flux, at constant line current density, j, flowing through the interface region is proportional to the interface area divided by line area ratio, δsw/(wh), or δs/h, where h is the line thickness. The Cu electromigration lifetime τ, is ΔL/Vd=ΔL h kT/(δsDsFe), where ΔL is the critical void length that causes failure, Vd is the void growth rate, Ds is the interface diffusivity, k is the Boltzmann constant, T is the absolute temperature and Fe is the electromigration driving force at the interface. ΔL is generally equal to the inter-level via size. The above equation shows that the lifetime is controlled by the interface diffusivity, Ds. To fully utilize Cu chips as the feature size is scaled to smaller dimensions (which causes higher current densities and even more electromigration), the fast diffusion pathway along interfaces, Ds, must be altered. The intents and purposes of this invention are to modify the property of the top surface of Cu lines in a damascene structure such that fast diffusion can be reduced. This will result in increased circuit lifetime (reliability) due to reduced electromigration or stress-induced failures.
In Cu damascene processing, U.S. Pat. Nos. 4,954,142, 4789,648, and 4,702,792, vias and trenches are etched in an insulator material, metal is deposited to fill these cavities, and chemical mechanical polishing (CMP) is used to remove the excess metal and form metal vias and lines. The metal fill: metal liner, Cu seed layer and Cu main conductor, are produced by a combination of physical vapor deposition and electroplating deposition techniques. The Cu interconnects (lines and vias) are embedded in a dielectric. Hu et al. (Thin Solid Films, 262, p. 84-92, 1995) reported that the Cu interconnections require metal and insulator adhesion/diffusion barrier layers in addition to main Cu conductors. U.S. Pat. No. 6,342,733 discloses the use of an electroless selective deposition film on the top of the Cu surface from a selective group of CoWP, CoSnP, CoP, Pd, CoB, CoSnB, In, NiB and W for reduced electromigration and stress induced migration of Cu wires. E. G. Colgan reported a selective CVD-W film for capping Cu damascene lines (Thin Solid Films, 262, p. 120-123 (1995)) for suppressed Cu hillock formation and oxidation protection. U.S. Pat. No. 5,447,599 teaches the use of Ti/Cu and Cu(Ti) alloy to form TiN(O) by thermally annealing and selective wet etching. U.S. Pat. No. 5,447,887 teaches the use of Cu silicide for improved adhesion between Cu and silicon nitride. U.S. Pat. No. 5,693,563 teaches an etch stop method for a Cu damascene process using a blanket film TiN 50 to 200 nm thick, on the top of a Cu damascene line, followed by patterning TiN using photo-resist and then etching. U.S. Pat. No. 5,968,333 extends the common electroplating method of using pure Cu to fill the trenches/holes to the use of a Cu(Al) alloy. U.S. Pat. No. 6,136,707 discloses the use of multiple Cu seed layers with various deposition techniques for improving main conductor electroplating in Cu or Ag processes. U.S. Pat. No. 6,181,012 teaches the use of Cu alloy seed layer for improving electromigration resistance, and the adhesion/surface properties of Cu interconnections. U.S. Pat. No. 5,023,698 discloses the use of copper alloys containing at least one alloying element selected from group of Al, Be, Cr, Mg, Ni Si, Sn and Zn. U.S. Pat. No. 5,077,005 discloses the use of copper alloys containing at least one alloying element selected from group of In, Cd, Sb, Bi, Ti, Ag, Sn, Pb, Zr and Hf where the weight percent of the alloying element used is between 0.0003 to 0.01. U.S. Pat. No. 5,004,520 discloses the use of a copper foil for film carrier applications containing at least one alloying element selected from group of P, Al, Cd, Fe, Mg, Ni, Sn, Ag, Hf, Zn, B, As, Co, In, Mn, Si, Te, Cr and Zn with impurity concentration from 0.03 to 0.5 weight percent. U.S. Pat. No. 4,749,548 discloses the use of copper alloys containing at least one alloying element selected from group of Cr, Zr, Li, P, Mg, Si, Al, Zn, Mn, Ni, Sn, Be, Fe, Co, Y, Ce, La, Nb, W, V, Ta, B, Hf, Mo and C to increase the strength of the copper alloys. However, none of this prior art discloses the use of Cu interconnections constructed by directly depositing very thin layers of 0.5 to 5 nanometers on the top Cu surface from a selected group of metal elements having both a high negative reduction potential with oxygen and the ability to form compounds with copper. The use of this new innovation will sufficiently improve the Cu interconnects so that Cu ULSI on-chip wiring can be extended to future generations.